High Bandwidth Flash (HBF): The Emerging NAND Tier Beneath HBM for AI Accelerators Preview
A research report on architecture, packaging, vendor roadmaps, and system implications. Prepared July 2026 by Shimogoryo Base; information horizon: public disclosures through early July 2026, live-verified 8–9 July 2026. Published 9 July 2026.
What this report covers
This free preview shows the executive framing, the full table of contents, and an excerpt of Section 1. The full report runs 12 sections plus source and verification appendices; every load-bearing claim carries an inline source link and a confidence label.
High Bandwidth Flash (HBF) is a proposed memory device class that stacks 3D NAND flash dies with through-silicon vias (TSVs) over a base logic die — in the physical idiom of High Bandwidth Memory (HBM) — to deliver HBM-class read bandwidth at NAND-class capacity and cost, packaged on or near an AI accelerator. It is aimed squarely at the economics of AI inference, where memory capacity and bandwidth, not FLOPs, are the binding constraints: trillion-parameter model weights, exploding KV caches at 100K–1M-token contexts, and read-mostly retrieval corpora all want terabytes within a microsecond of the GPU — a rung of the memory pyramid that nothing currently serves.
Why now. SanDisk introduced HBF at its "Future FWD" Investor Day in February 2025 and signed a memorandum of understanding with SK hynix on 6 August 2025 to jointly standardize it. In February 2026 the two companies converted the MoU into a formal "HBF Spec. Standardization Consortium" with a dedicated workstream under the Open Compute Project (OCP). Headline claims: 8–16x the capacity of HBM per stack at comparable cost (~512 GB per stack versus 24–64 GB for HBM3E/HBM4), 1.6 TB/s Gen1 read bandwidth, an accelerator with 8 HBF stacks presenting ~4 TB of directly attached memory, first memory samples in 2H 2026, and samples of the first AI inference devices using HBF in early 2027. The report weighs each of these claims against primary sources — and against the engineering realities of NAND read latency, write asymmetry, endurance, thermals, and the scarce "shoreline" of xPU die edge that HBF must share with HBM.
How the report is built. Every claim is labeled [Confirmed] (multiple public sources / vendor statements), [Reported] (single-source or trade-press reporting), [Analyst speculation] (third-party projection), or [Author analysis] (this report's own inference). All load-bearing claims were live-verified against primary sources on 8–9 July 2026, with a claim-by-claim verification log appended, and the final text was hand-reviewed and hand-edited by the Shimogoryo Base principal analyst, who has conducted research into memory and storage tiers optimized for inference.
Table of contents (full report)
- What Is HBF and Why Now
- How the NAND Itself Will Be Structured
- Will HBF Require Unique Wafers?
- How It Will Be Attached
- Where It Will Be Attached
- What HBF Means for HBM Systems
- The Beachfront (Shoreline) Question
- Vendor-by-Vendor State of the Art
- Competing and Adjacent Approaches
- What the Academic Literature Signals
- Risks and Open Questions
- Conclusion and Outlook Table
Plus: Appendix A — principal sources referenced (with URLs); Appendix B — claim-by-claim verification log (8 July 2026); full disclosures and license terms. Vendor-by-vendor coverage: SanDisk, SK hynix, Samsung, Micron, Kioxia, Huawei, YMTC, CXMT.
Excerpt — Section 1: What Is HBF and Why Now
High Bandwidth Flash (HBF) is a proposed memory device class that stacks 3D NAND flash dies with through-silicon vias (TSVs) over a base logic die — in the physical idiom of High Bandwidth Memory (HBM) — to deliver HBM-class read bandwidth at NAND-class capacity and cost, packaged on or near an AI accelerator. The concept was introduced publicly by SanDisk at its "Future FWD" Investor Day in February 2025, held as it completed its separation from Western Digital [Confirmed], and was elevated from a single-vendor initiative to a would-be industry standard when SanDisk and SK hynix signed a memorandum of understanding on August 6, 2025 to jointly define an HBF specification and build an ecosystem around it [Confirmed]. In February 2026 the two companies converted the MoU into a formal "HBF Spec. Standardization Consortium," launching a dedicated workstream under the Open Compute Project (OCP) to make HBF a global open standard [Confirmed].
SanDisk's headline claims at introduction, repeated at the Future of Memory and Storage (FMS) conference in August 2025 (where HBF won the FMS "Best of Show — Most Innovative Technology" award in the NAND flash category [Confirmed]):
8–16x the capacity of HBM per stack at comparable cost per stack — SanDisk has cited on the order of 512 GB per HBF stack, versus 24–36 GB for HBM3E and roughly 48–64 GB for HBM4-generation stacks [Confirmed]. Read bandwidth "comparable to HBM" — achieved through massive on-die parallelism rather than fast individual cells. SanDisk has since put a number on Gen1: 1.6 TB/s per stack, which it describes as "more than 50x faster than top-tier PCIe 5.0 SSDs" — below leading-edge HBM4 (~2–2.8 TB/s) but far above any SSD, with multi-generation scaling planned [Confirmed]. An accelerator with 8 HBF stacks could present ~4 TB of directly attached memory, versus ~192–288 GB for 8 stacks of HBM3E [Confirmed]. Roadmap: first HBF memory samples in the second half of 2026, and samples of the first AI inference devices using HBF in early 2027 [Confirmed].
The motivation is the shift of AI economics from training to inference, where the binding constraints are memory capacity and memory bandwidth rather than FLOPs: model weights keep growing, long-context and agentic inference makes the KV cache a first-order memory consumer, HBM is the most expensive commodity memory per bit ever shipped in volume while NAND is roughly one to two orders of magnitude cheaper per bit, and inference is fundamentally read-mostly — a workload shape that tolerates NAND's limited write endurance while exploiting its density. [Author analysis] HBF is best understood not as "flash replacing HBM" but as the industry attempting to formalize a new, nonvolatile rung of the memory pyramid: HBM for the hot, write-intensive working set; HBF for warm, read-mostly capacity (weights, KV/prefix caches, embeddings, RAG corpora); SSD for cold bulk…
The full report continues with the NAND die re-architecture required to hit HBM-class bandwidth (mini-array parallelism, CBA/wafer-bonded logic, SLC media and read-latency targets, TSV stacking), the unique-wafer and fab-economics question, attach and placement options from HBM-site 2.5D to hybrid HBM+HBF stacks, the shoreline allocation fight, the complete vendor-by-vendor state of the art, the 2025–2026 academic literature (H3, HAVEN, MemExplorer, NVLLM, KVNAND, KAIST TERALAB), nine enumerated risks and open questions, and a dated adoption timeline through 2030.
This is a free preview
The full report includes all 12 sections — NAND die architecture, unique-wafer economics, attach and placement analysis, the shoreline question, vendor-by-vendor coverage of SanDisk, SK hynix, Samsung, Micron, Kioxia, Huawei, YMTC and CXMT, competing approaches, the academic literature synthesis, risks, and the conclusion and outlook matrix — plus Appendix A (principal sources with URLs) and Appendix B (the claim-by-claim verification log). Purchase the full report (HTML + PDF, delivered instantly, single-seat license) — $500.
Method and limitations
Prepared July 2026 from public reporting, vendor announcements, and conference disclosures (SanDisk Investor Day, FMS 2025, OCP Global Summit 2025, vendor press releases, trade press, and academic preprints). Every load-bearing claim was live-verified against primary sources on 8–9 July 2026; sources are cited inline as clickable URLs and each claim carries a confidence label ([Confirmed] / [Reported] / [Analyst speculation] / [Author analysis]).
The final report was hand-reviewed and hand-edited by the Shimogoryo Base principal analyst. It contains forward-looking statements that are inherently uncertain; it is provided for general informational purposes only and is not investment, legal, or engineering advice. See the full disclosures inside the report.